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Case Studies

Work we've been part of.

A look at some of the programs we've contributed to — the areas we worked in, and how we engaged.

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Silicon Engineering
Embedded Engineering for a Next-Generation Silicon Program
Contributed across silicon validation, ML compiler stack development, and test automation — embedded within the client's team across the full delivery lifecycle.
Silicon Validation ML Compiler Test Automation Embedded Partnership
FPGA Engineering
Porting a Machine-Vision Pipeline Across FPGA Generations
Migrated a production grain-sorting vision pipeline from Spartan-II to Kintex-7 — updating two HDL stages, redesigning sensor and ejection I/O, and cutting over without interrupting production throughput.
FPGA Migration HDL / Verilog Machine Vision Grain Sorting
Case Study · Silicon Engineering · Embedded Partnership

Embedded Engineering for a
Next-Generation Silicon Program

YantraVision contributed across silicon validation, ML compiler stack development, and test automation — working within the client's team and processes across a multi-phase silicon program.

Silicon Engineering Case Study
1000+Test cases in regression
2Silicon environments
3Engineering tracks
Multi‑phaseProgram coverage
End‑to‑endValidation pipeline
Program Context

An on-device AI compute architecture,
built for inference at the edge.

The client was developing a next-generation silicon architecture designed to run machine learning workloads on-device, without reliance on cloud infrastructure. The program covered the full silicon lifecycle — from architecture definition and pre-silicon modelling through to post-silicon bring-up and production validation.

The scope included the silicon itself, the software stack that exposes it to ML frameworks, and the validation infrastructure that covers both environments. YantraVision was brought in to contribute across all three areas, working as part of the client's engineering organisation rather than as an external delivery stream.

"We worked within their team — using their tools, their processes, and their workflows. The work was assigned, reviewed, and delivered the same way as any internal contribution."

How We Worked

Integrated into the team,
not alongside it.

The engagement model was embedded from the start. Work was tracked in the client's issue management system, reviewed through their code review process, and delivered against their release milestones. There was no separate project management layer or dedicated interface between YantraVision engineers and the client's teams.

Engineers worked directly with counterparts in the client's silicon validation, compiler, and test infrastructure teams. Handoffs were direct. Decisions were made in the same rooms — or on the same calls — as the client's own engineers. This applied across all three workstreams throughout the program.

Areas of Work

Three workstreams,
running in parallel across the program.

01
Silicon Validation Work covered the full validation lifecycle for the compute architecture — architecture review, test plan definition, test case development, and execution across both pre-silicon and post-silicon environments. The validation application developed during this track supported functional correctness testing, performance characterisation, power analysis, and benchmarking against defined targets. Coverage was maintained across both simulation and physical silicon, with results feeding directly into the client's sign-off process.
02
ML Compiler Stack Contributions were made to selected modules within the client's ML compiler stack — the software layer responsible for taking models from standard ML frameworks and compiling them for execution on the target silicon. Work focused on correctness of model compilation, execution efficiency on-device, and performance of models running through the stack. This was done in direct coordination with the client's architecture and runtime teams, with changes integrated through the standard review process.
03
Test Automation & Regression A regression and automation framework was built to run over a thousand test cases on a daily and weekly cadence across both pre- and post-silicon platforms. The framework was structured to enable fast triage of regression failures — with results organised by test category, environment, and failure type. It was integrated into the client's existing validation workflows and used by both YantraVision and client engineers as a shared resource throughout the program.
Program Span

Across multiple phases,
from pre-silicon through to production readiness.

The engagement covered multiple phases of the silicon program. Work began during the pre-silicon phase, where the focus was on simulation environments, architecture-level validation, and building the automation infrastructure that would carry through to physical silicon. As the program moved into post-silicon bring-up, the same frameworks and test cases were ported and extended to run on physical devices.

Each phase brought changes in scope and priority, and the contribution areas shifted accordingly. Silicon validation activity increased significantly during post-silicon bring-up. Compiler stack contributions were concentrated in the mid-phase, around stabilisation. Test automation work ran throughout and was maintained across both environments simultaneously.

Phase 1
Pre-Silicon
Architecture review, test plan definition, simulation environment setup, automation framework foundations, and initial compiler module work.
Phase 2
Post-Silicon Bring-Up
Test case porting to physical silicon, bring-up validation, power and performance characterisation, regression framework extension to cover device environments.
Phase 3
Production Validation
Full regression suite execution, coverage closure, benchmarking against production targets, and final validation sign-off support across the full test matrix.
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Case Study · FPGA Engineering · Grain Sorting

Porting a Machine-Vision Pipeline
Across FPGA Generations

Migrated a production grain-sorting vision pipeline from Spartan-II to Kintex-7 — updating two HDL stages, redesigning sensor and ejection I/O, and cutting over with zero interruption to production throughput.

FPGA Migration Case Study
2FPGA boards replaced
2HDL stages rewritten
0Production interruptions
Kintex-7Target platform
The Problem

End-of-life silicon, no drop-in replacement

The client's grain-sorting machines ran a custom FPGA pipeline built on Xilinx Spartan-II — a platform that had reached end-of-life. Spare boards were running out, and any hardware failure would halt the production line with no replacement path. A migration was unavoidable, but the pipeline was processing live grain streams at pixel-rate speeds with tight real-time constraints.

The risk was compounded by incomplete documentation. The original HDL had been written by engineers who were no longer available, and two of the pipeline stages had undocumented timing dependencies between them.

What We Did

Reverse-engineer, port, validate — without stopping production

YantraVision began with a full audit of the existing HDL — tracing every signal path, documenting timing assumptions, and identifying the two stages with undocumented inter-stage dependencies. We then selected Kintex-7 as the target platform.

The port was done in two phases: sensor interface and pixel acquisition (updated for Kintex-7 LVDS I/O), then ejection control (GPIO remapped, ejector timing preserved). Both stages were validated against recorded pixel streams before any hardware was swapped. Cutover was done during a scheduled maintenance window with no production interruption.

System Hardware

The full signal chain — camera to ejector

The grain-sorting pipeline spans four hardware layers. Only the FPGA processing board changed during migration; the Basler camera and Silicon Software microEnable frame grabber upstream, and the ejector bank downstream, were preserved in-place.

Imaging
Basler
Line-scan camera
Pixel-rate grain stream capture
Frame Grabber
Silicon Software
microEnable
Camera data → FPGA pipeline
Processing ← migrated
Kintex-7 FPGA
Spartan-II → Kintex-7
2 HDL stages rewritten
Output
Pneumatic Ejectors
GPIO-driven
Sub-ms timing precision
Outcome

Production continuity. Zero sorting errors on cutover.

The migrated pipeline met all original throughput and accuracy specifications on first production run. The client now runs on a supported platform with a clear upgrade path for future Kintex generations.