High level synthesis (HLS) tools, like XILINX Vivado HLS, can provide significant benefits for implementing algorithms like signal processing and image processing on FPGAs. These tools enable development and testing of hardware-based algorithms using higher level languages (like C++) before implementing, verifying and validating using HDL. This is because algorithm development, and in particular testing, is much easier to perform on higher level languages like C/C++ than it is directly using HDL. The higher-level representation enables algorithms to be expressed more easily, significantly reducing algorithms development times. On down side the higher-level languages don’t provide sufficient design space exploration between resources, performances and latencies. It is a tedious exercise to recode complex algorithms as HDL/RTL. This, coupled with the large software code base of image processing algorithms, has led to development of compilers which can directly synthesise the RTL hardware from the high-level software designs. It is this characteristic that is the basis of many of the advantages of high-level synthesis (HLS).

Modern HLS tools, like XILINX Vivado HLS, generally perform the following steps: dataflow analysis (Identify operations that need to be performed); resource allocation (Assess the number of hardware operators required to execute all of the source code operations); resource binding (Allocate source code operations to hardware resources); and scheduling (Schedule when each source code operation is executed on the allocated hardware).

Benefits of using HLS

With high level synthesis, code can be relatively easily ported from software to a hardware implementation. However, simply compiling software code for FPGA is not sufficient. The software algorithm has often been optimised for implementation on a CPU based processor. It is usually necessary to restructure the algorithm for it to better suit FPGA hardware. However, rather than optimize the algorithm manually, with HLS this restructuring can be performed directly on the high-level source, which is easier and less error prone. One of the key benefits of HLS tools is its ability to analyse the structure of the algorithm (loops, branches, etc.) to automatically extract and build the control path. In contrast with this, manual implementation in RTL requires explicitly coding the control path as well as the data path. For complex algorithms, designing the control path can take as much effort as designing the data path.

Modern synthesis tools are able to exploit parallelism in three main ways:

• By performing a dataflow analysis to determine data dependencies. From this, the processing sequence can be inferred, and pipelined if necessary, to meet desired timing constraints.
• By analysing loops which involve significant processing with limited dependencies between iterations. This enables a pipelined architecture to be inferred, where a subsequent iteration can be started before the previous iteration has completed. Such processing fits well with a streamed type of architecture.
• By unrolling loops. Multiple parallel hardware blocks are built to enable the iterations to be parallelised.

Case Study: Our experience using HLS for Image Processing Application

In our real-time experience with one of our clients in the high-speed sorting OEM Industry, the customer wanted to enhance the image processing algorithms to meet the needs of the market. The original design included microcontrollers that were only capable of performing simple thresholding techniques restricting the quality of inspection. We implemented an image processing algorithm with a FPGA processor exploiting parallelism to achieve more complex image processing within the same cycle time. These algorithms were developed and tested using C++ before using HLS in Vivado toolchain to convert into HDL for porting into the FPGA processor. Click here (share case study link) to read the case study in detail.

Reference: Article titled ‘The advantages and limitations of high-level synthesis for FPGA based image processing’ written by Donald G. Bailey, School of Engineering and Advanced Technology, Massey University, Palmerston North, New Zealand

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